1. Field of the Invention
The present disclosure generally relates to integrated circuits, and, more particularly, to the highly sophisticated integrated circuits including transistor structures of different threshold voltages.
2. Description of the Related Art
The manufacturing process for integrated circuits continues to improve in several ways, driven by the ongoing efforts to scale down the feature sizes of the individual circuit elements. A key issue in developing integrated circuits of increased packing density and enhanced performance is the scaling of transistor elements, such as MOS transistor elements, to increase the number of transistor elements in order to enhance performance of modern CPUs and the like with respect to operating speed and functionality. One important aspect in manufacturing field effect transistors having reduced dimensions is the reduction of the length of the gate electrode that controls the formation of a conductive channel separating the source and drain regions of the transistor. The source and drain regions of the transistor element are conductive semiconductor regions including dopants of an inverse conductivity type compared to the dopants in the surrounding crystalline active region, which may also be referred to as a substrate or a well region.
Although the reduction of the gate length is necessary for obtaining smaller and faster transistor elements, it turns out, however, that a plurality of issues are additionally involved to maintain proper transistor performance for a reduced gate length. For example, so-called short channel effects may occur for highly scaled transistor elements, resulting in a reduced controllability of the channel region, which may cause increased leakage currents and generally degraded transistor performance. One challenging task in this respect is, therefore, the provision of appropriately designed junction regions in the form of shallow junctions at least at the area in the vicinity of the channel region, i.e., source and drain extension regions, which nevertheless exhibit a moderately high conductivity so as to maintain the resistivity in conducting charge carriers from the channel to a respective contact area of the drain and source regions at a relatively low level, while also the parasitic drain/source capacitance and the electric field are to be taken into consideration. The requirement for shallow junctions having a relatively high conductivity while providing adequate channel control is commonly met by performing an ion implantation sequence on the basis of a spacer structure so as to obtain a high dopant concentration having a profile that varies laterally and in depth. The introduction of a high dose of dopants into a crystalline substrate area, however, generates heavy damage in the crystal structure, and, therefore, one or more anneal cycles are typically required for activating the dopants, i.e., for placing the dopants at crystal sites, and to cure the heavy crystal damage. However, the electrically effective dopant concentration is limited by the ability of the anneal cycles to electrically activate the dopants. This ability in turn is limited by the solid solubility of the dopants in the silicon crystal and the temperature and duration of the anneal process that are compatible with the process requirements. Moreover, besides the dopant activation and the curing of crystal damage, dopant diffusion may also occur during the annealing, which may lead to a “blurring” of the dopant profile. This effect may be advantageous in some cases for defining critical transistor properties, such as the overlap between the extension regions and the gate electrode, and also for reducing the overall capacitance of the PN junctions by increasing the depth of the deep drain and source areas, for instance, in silicon-on-insulator (SOI) devices, the drain and source areas may extend down to the buried insulating layer with a desired high concentration. Therefore, for highly advanced transistors, the positioning, shaping and maintaining of a desired dopant profile are important properties for defining the final performance of the device, since the overall series resistance of the conductive path between the drain and source contacts, as well as the controllability of the channel region, may represent a dominant aspect for determining the transistor performance.
Moreover, other important transistor characteristics may presently also be adjusted on the basis of the complex dopant profile in the active regions of the transistor elements. For example, the threshold voltage of a transistor, i.e., the voltage applied between the gate electrode and the source terminal of the transistor element, at which a conductive channel forms in the channel region, is a transistor characteristic that substantially affects overall transistor performance. Typically, the ongoing shrinkage of critical dimensions of the transistors may also be associated with a continuous reduction of the supply voltage of electronic circuitry. Consequently, for performance driven transistor elements, the corresponding threshold voltage may also have to be reduced in order to obtain a desired high saturation current at a reduced gate voltage, since the reduced supply voltage may also restrict the available voltage swing for controlling the channel of the transistor. However, the reduction of the threshold voltage, which may typically be accomplished by appropriately doping the well region of the transistor in combination with sophisticated halo implantation processes, which are designed so as to provide the appropriate dopant gradient at the PN junctions and for the overall conductivity of the channel region, may also affect the static leakage currents of the transistors. That is, by lowering the threshold voltage, typically the off current of the transistors may increase, thereby contributing to the overall power consumption of an integrated circuit, which may comprise millions of corresponding transistor elements. In addition to increased leakage currents caused by extremely thin gate dielectric materials, the static power consumption may result in unacceptable high power consumption, which may not be compatible with the heat dissipation capabilities of integrated circuits designed for general purposes. In an attempt to maintain the overall static leakage currents at an acceptable level, complex circuitries are typically designed so as to identify speed critical paths and selectively form transistors of the speed critical paths so as to have a low threshold voltage, while less critical signal paths may be realized on the basis of transistors of higher threshold voltages, thereby reducing static leakage currents while, however, also reducing switching speed of these transistors. For example, in modern central processing units (CPU), several different “flavors” of transistors may be employed in order to take into consideration the different hierarchy with respect to signal processing speeds.
For example, generally, high performance transistors, i.e., transistors having a very thin gate dielectric material, may, thus, be implemented with different transistor characteristics depending on the overall circuit layout and design. For instance, the different transistor characteristics may result in devices differing in gate leakage, off-current, threshold voltage and the like. Typically, these different characteristics may be implemented on the basis of an appropriate implantation regime when incorporating the well dopant species prior to patterning the gate electrode structures. Hence, the well dopant implantation sequence for N-channel transistors and P-channel transistors may be performed such that a well implantation may provide a basic well dopant concentration, which may be considered as a regular well dopant profile, while any other “flavors” may then be established by performing any further well implantation processes based on the same or a counter doping species, thereby increasing or reducing the overall conductivity in the corresponding well regions.
As discussed above, upon further scaling the overall transistor dimensions, short channel effects are frequently taken into consideration by additionally modifying the basic well dopant concentration in order to appropriately adjust the resulting threshold voltage of these short channel transistors. To this end, at an appropriate manufacturing stage, the maximum well dopant concentration may be locally increased by performing appropriate implantation processes so that a dopant species is incorporated that is counter-doping relative to the drain and source dopant species that are incorporated in the drain and source areas. Frequently, the corresponding implantation sequence is applied after patterning the gate electrode structures in order to obtain the locally increased well dopant concentration in a self-aligned manner with respect to the gate electrode structure. Also, in this manufacturing phase, the drain and source extension regions are typically implanted by using the gate electrode structures as an implantation mask in combination with appropriately configured offset spacer elements. Consequently, a moderately complex implantation sequence is required in this manufacturing phase, since, for instance, typically the locally increased dopant concentration, which is also referred to as a halo implantation, may have to be performed on the basis of a tilt angle, typically from two opposite sides of the transistor device. Furthermore, since the threshold voltage adjustment may have to be performed differently for the various transistors, correspondingly adapted halo implantation sequences may have to be applied.
Moreover, the continuous reduction of the channel length of sophisticated transistors may also require additional measures since, as discussed above, the static and dynamic leakage currents may exponentially increase, thereby failing to meet the thermal design power requirements of many circuits. For example, upon further reducing the channel length, typically an increased capacitive coupling of the gate electrode to the channel region is required, thereby necessitating an adaptation of a thickness of the gate dielectric material and/or the dielectric characteristics thereof. In most recent developments, a further reduction of the thickness of well-established gate dielectric materials, such as silicon oxynitride and the like, which may be provided with a thickness of 1.5 nm, may no longer be compatible with static power consumption requirements, so that a gate dielectric material may at least partially be provided in the form of a so-called high-k dielectric material, which is to be understood as a dielectric material having a dielectric constant of 10.0 or higher. For example, a plurality of metal oxide-based materials and silicates, for instance hafnium oxide, hafnium silicon oxide and the like, may frequently be used as a replacement material or in combination with a conventional very thin silicon oxide-based material, thereby providing the required capacitive coupling, while at the same time keeping the leakage currents at an acceptable level. Furthermore, these high-k dielectric materials may have to be provided in combination with appropriate metal-containing electrode materials since typically highly doped polysilicon may no longer have an appropriate work function so as to obtain the desired threshold voltage for N-channel transistors and P-channel transistors, respectively. To this end, appropriate metal species, such as titanium, tantalum, lanthanum, aluminum and the like, may be formed on or above the high-k dielectric material in order to obtain the desired electronic characteristics and also provide superior conductivity of the gate electrode material, at least in the vicinity of the gate dielectric material, thereby additionally avoiding the presence of a depletion zone, which may typically build up in a polysilicon-based electrode material in complex gate electrode structures.
In some sophisticated approaches, the high-k dielectric material in combination with an appropriate work function electrode material may be provided in an early manufacturing stage, i.e., upon patterning the gate electrode structure, thereby avoiding complex patterning and etch sequences in a late manufacturing stage, i.e., so-called replacement gate approaches in which the high-k dielectric material or at least the work function adjustment may be accomplished after completing the basic transistor configuration and after any high temperature processes.
It turns out, however, that the threshold voltage adjustment in an early manufacturing stage may require the incorporation of an appropriate channel material in some types of transistors in order to achieve a desired band gap offset, for instance with respect to P-channel transistors and N-channel transistors. To this end, in sophisticated approaches, an appropriate semiconductor alloy, such as a silicon/germanium alloy, is formed in or on the active region of one type of transistor, while other active regions are masked by an appropriate hard mask material. In this manner, an appropriate composition and thickness of the threshold voltage adjusting semiconductor alloy may be obtained, for instance, for P-channel transistors, thereby enabling a process strategy in which sophisticated high-k metal gate electrode structures may be formed so as to include the high-k dielectric material, the work function metal species and any metal-containing electrode materials, without requiring any modifications of the gate electrode structures in a later manufacturing stage. Consequently, in conventional sophisticated patterning strategies, the active regions of P-channel transistors receive the silicon/germanium alloy, while a required further adaptation of the threshold voltages of, for instance, transistors of extremely short channel, which is to be understood as a channel length of 50 nm and less, and transistors having a longer channel, that is, a channel length of above 50 nm, may be accomplished by applying additional implantation processes in a self-aligned manner, i.e., after the patterning of the gate electrode structures. For example, as explained above, corresponding halo implantation sequences may be applied so as to locally increase the basic well dopant concentration in order to appropriately adjust the threshold voltages of short channel transistors and “long” channel transistors. On the other hand, the incorporation of an additional well dopant species may, however, significantly affect the overall transistor performance, since the additional well dopant species may also be incorporated in drain and source areas, thereby reducing the effective degree of doping therein, which may have a particular influence on the short channel transistors, since frequently any reduction of the overall transistor dimensions may also require a reduction of the dopant concentration in the drain and source areas. Hence, the overall conductivity of the short channel transistors may be significantly influenced by the incorporation of halo regions which, in turn, are required in conventional strategies in order to obtain the desired threshold voltage in combination with the previously provided silicon/germanium alloy and the sophisticated high-k metal gate electrode structure.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.